This invention relates to multi-channel digital-to-analog (D/A) converters comprising a plurality of D/A converter units of the current cell type. More in detail, this invention relates to such multi-channel D/A converters structured by taking into consideration the variations in the conversion characteristics of the individual D/A converter units. In order to uniformize the conversion characteristics of the individual D/A converter units, undesirable ill-effects of parasitic resistances in the conductive lines to each of the D/A converter units are eliminated.
FIG. 5A shows an example of prior art D/A converter unit 10 of the current cell type, representing a basic D/A converter unit for one-channel operation for converting one digital input DR into one analog output AR, comprising a plural n-number (determined by 2.sup.m) of current mirrors where m is the number of bits of the digital input DR. Explained more in detail, this converter unit 10 comprises n pairs of transistors Tr10+Tr11, Tr10+Tr12, . . . , Tr10+Tr1n forming current mirrors and a decoder 14 (or a selecting means) for decoding the digital input DR and outputting selection signals to the individual current mirrors. The total current outputted from those of the transistors Tr11-Tr1n which were selected by the selection signals serves as the analog output AR. In other words, a plurality of current mirrors and the currents outputted therefrom are selectively reflected in the analog output AR, and this is how the analog output AR is generated, corresponding to the digital input DR.
Explained further in detail, the transistor Tr10 is a MOS transistor on the input side of the current mirrors, its drain being connected to a source line 11, its source being connected to a steady current source 13 for a reference current i10, and its gate being connected to the gate of each of the other transistors Tr11-Tr1n. Thus, the transistor Tr10 may be referred to as the input transistor, serving to output a steady reference current.
The transistor Tr11 is another MOS transistor on the output side of one of the current mirrors, its drain being connected to the source line 11 and its source, through which a mirror current i11 flows, being connected through a switch SW11 to an output line for outputting the analog output AR. Each of the other transistors Tr12-Tr1n is similarly a MOS transistor serving as the output transistor of a corresponding one of the current mirrors, its drain being connected to the source line 11 and its source, through which a mirror current i12, i13, . . . , or i1n flows, being connected through a switch SW12, SW13, . . . , or SW1n to the output line. In summary, the transistors Tr11-Tr1n are a plurality of output transistors having a single input transistor Tr10 to together form n current mirrors which are partially in common. Depending on whether the individual switches SW11-SW1n are closed (ON) or open (OFF), the output currents i11-i1n from these current mirrors may or may not be included in the analog output AR. It is the decoder 14 that controls the opening and closing of these switches, causing a proper number of switches to be opened, depending on the digital input DR. As the value of the digital input DR increases sequentially from "0" to "1", "2", . . . and "n", the decoder 14 normally switches on (closes) the switches SW11, . . . and SW1n in a specified order. As the value of the digital input AD is reduced sequentially, the switches are opened also sequentially in the reverse order.
A multi-channel D/A converter requires not only one but a plurality of such D/A converter units. When a color image has been subjected to a digital signal processing according to the three basic colors RGB, for example, a three-channel D/A converter is used for generating an analog output and transmitting to a monitor or the like.
FIG. 5B shows an integrated circuit (IC) 1 providing such a multi-channel D/A converter having three D/A converter units as described above for three channels integrated on one chip. In this example, the multi-channel D/A converter 1 is shown as having a cell-type D/A converter unit as described above and illustrated at 10 in FIG. 5A, another similarly structured D/A converter unit 20 adapted to convert a digital input DG into an analog output AG and still another similarly structured D/A converter unit 30 adapted to convert a digital input DB into an analog output AB. Let us assume that each of these digital inputs DR, DG and DB assumes 6 bits and n=63.
Such a multi-channel D/A converter 1 requires three power terminals for supplying source voltage Vdd and three grounding terminals GND are required in addition to the output terminals for the analog outputs AR, AG and AB. When the multi-channel D/A converter 1 thus structured is mounted to a printed circuit board, for example, the three power terminal and the three grounding terminals are usually connected individually together through wiring outside the multi-channel D/A converter 1. Because of the large number of terminals, the IC package cannot be sufficiently miniaturized and the printed wiring becomes undesirably complicated.
In view of the above, it may be proposed to connect conductive lines such as power source lines and reference voltage lines connecting between the individual converter units within the multi-channel D/A converter such that one power source terminal for the source voltage Vdd and one grounding terminal can be shared among the three D/A converter units. FIG. 6 shows another integrated circuit 2 of a multi-channel D/A converter thus structured, indicating corresponding components by the same numerals as in FIG. 5B. In FIG. 6, the components of the converter units 20 and 30 that correspond to those of the converter unit 10 are each indicated by a symbol obtained by adding respectively 10 or 20 to that of the corresponding component of the converter unit 10. In FIG. 6, numeral 60 indicates an image signal processing circuit, as an example of circuit which may be also integrated, for generating the digital input DR, DG and DB to be transmitted to the individual converter units 10, 20 and 30 from a received composite image signal CMP.
Explained more in detail, trunk power source lines for the individual (first, second and third) converter units 10, 20 and 30 are respectively indicated by numerals 11, 21 and 31, and grounding lines for the three converter units 10, 20 an 30 are respectively indicated by numerals 12, 22 and 32. The trunk power source line 21 for the second converter unit 20 is connected to the trunk power source line 11 to the first converter unit 10 through a branch power source line 41, but the trunk power source line 31 for the third converter unit 30 is connected not to the trunk power source line 11 to the first converter unit 10 but to the aforementioned branch power source line 41 to the second converter unit 20 through another branch power source line 42. Similarly, the grounding line 11 of the first converter unit 10 is directly connected to the grounding terminal GND but the grounding line 22 of the second converter unit 20 is connected not directly to the grounding terminal but through a connecting line 51 to the grounding line 12 of the first converter unit 10, and the grounding line 32 of the third converter unit 30 is connected through another connecting line 53 to the grounding line 22 of the second converter unit 20.
Thus, parasitic resistances Ra-Rn to the trunk power source lines 11, 21 and 31 through which relatively large currents flow, as well as parasitic resistances R1, R2, R3 and R4 to the branch power source lines and to the connecting lines through which, too, fairly large currents flow, affect the conversion characteristics of the converter units 10, 20 and 30 adversely. These adverse effects usually appear in the form of lowered analog outputs, especially from converter units of the later stages (positioned farther away from the power source terminal where the source voltage Vdd is applied) containing more parasitic resistances. This is schematically illustrated by the input-output characteristic diagram of FIG. 7 showing that the characteristic curve for the second converter unit 20 is lower than that of the first converter unit 10 and that the characteristic curve of the third converter unit 30 is even lower than that of the second converter unit 20, the difference being greater for larger values of digital input.
Since such differences in the conversion characteristics among the converter units cause irregularities in the color display and adversely affect the overall color quality of the displayed image, appropriate adjustment resistors R5 and R6 are inserted respectively on the trunk power source lines 11 and 21 to the first and second converter units 10 and 20 on the side towards the power source terminal. After the multi-channel D/A converter has been produced, its conversion characteristics are measured, and these adjustment resistors R5 and R6 are adjusted, say, by trimming, according to the result of the measurement such that the variations among the conversion characteristics of the converter units 10, 20 and 30 are controlled.
This kind of attempt at multi-channel D/A conversion is not satisfactory because it is a cumbersome process to adjust these resistors for all converter units.
Although not separately illustrated, there has also been an attempt to use a single converter unit sequentially with a plurality of pairs of digital input and analog output. Neither is this method satisfactory because if the number of channels is large, the sampling rate must be increased accordingly in order to maintain the same processing efficiency because a single converter unit must be shared time-wise.